1. Field of the Invention
The present invention relates to both a device and a method for accessing a cache memory based on a real address according to the memory access instruction of a virtual address (logical address) in an information processing apparatus with a logical address designation.
2. Description of the Related Art
In a cache memory system based on a logical address (or called “virtual address”), if there is a synonym problem, specifically, if a plurality of logical addresses point to the same real address, the same memory content must always be maintained in a location corresponding to each logical address in the cache memory, which is a troublesome problem in cache memory management.
When a cache memory system based on a real address (absolute address) is organized, time delay in the translation from a logical address to a real address becomes a problem.
Therefore, there is a solution in which a previous translation history from logical addresses to real addresses, called an “absolute address history table” is stored and by retrieving data from this table, the time delay is reduced.
According to this solution, in the case of operand access, the cache memory is retrieved based on a logical address obtained by adding a register value and a displacement value (in one case, the total of a plurality of register values and a displacement value, in another case, only a register value and in another case, only an immediate value (displacement value)). In this case, which register should be used, the displacement value (immediate value) and the like can be judged when an instruction is decoded. Therefore, if a register value is already determined, sometimes the absolute address history table can be retrieved by calculating a logical address, with time allowance.
However, according to an instruction control method, such as a superscalar method, an out-of-order method or the like, the relevant instruction is executed before register modification by an instruction string that is executed prior to the relevant instruction for operand access is determined. In this case, for example, the register value is bypassed from an arithmetic unit or a cache memory instead of reading the register value from a register file, and the relevant instruction is tentatively executed.
Alternatively, if function improvement by a recent high-clock or short-latency request is aimed for, sometimes it takes too much time to calculate a logical address and then to retrieve data from the absolute address history table even if the register value is determined.
Therefore, in such a case, even if a register value or a displacement value that is used is known, retrieving data from the register, calculating a logical address by adding up the values and retrieving data from the absolute address history table based on a logical address causes great function loss due to time delay.
However, since there is a tendency that a displacement value is small in the calculation of an operand address, first, in an architecture with a virtual memory, instead of separately locating a series of logical addresses in a real memory for each byte, a specific block (usually a powered value of 2) of logical addresses are collectively located properly in an real memory (hereinafter the minimum unit of this bock is called a “page”). For example, as shown in FIG. 1, since the low-order byte index of 20 bits or more of a real address is the same as that of a logical address, both a higher-order segment index (1 bit to 11 bits) and a higher-order page index (12 bits to 19 bits) are translated into a real address.
Therefore, it is not a low-order bit, that is, a byte index value, but higher-order bits (segment index and page index values) that are needed for cache access. Therefore, for a retrieval address, not the calculated address, but the middle-order bit part of a register value, which is the basis of the calculation, is used.
As described above, a problem in retrieving data from the table based on a register is page cross (carry) caused when adding a displacement value to a register value. A logically adjacent page is not always located adjacently. If carry occurs and a logically adjacent page is retrieved, cache retrieval always fails. Therefore, a time delay results.
However, it takes too much time to retrieve data from the absolute address history table using a result obtained by accurately adding a register value and a displacement value, including a case with a bypass, which is a problem.
There are also a variety of kinds of instruction fetch requests on an instruction fetch side. It also takes to much time to determine which instruction fetch request is issued from these many requests, to select a corresponding logical address and to retrieve data from the absolute address history table, which is also a problem.